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Section 3 MCU Operating Modes
Initial
Bit
Bit Name
Value
3
FLSHE
0
2
IICS
0
1
ICKS1
0
0
ICKS0
0
Rev. 1.00 May 09, 2008 Page 70 of 954
REJ09B0462-0100
R/W
Description
R/W
Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FCCS, FPCS, FECS, FKEY, FMATS, and
FTDAR), power-down state control registers (SBYCR,
LPWRCR, MSTPCRH, and MSTPCRL), and on-chip
peripheral module control registers (PCSR).
0: When RELOCATE is 0, control registers of power-
down state and peripheral modules are accessed in
an area from H'(FF)FF80 to H'(FF)FF87. Area from
H'(FF)FEA8 to H'(FF)FEAE is reserved.
When RELOCATE is 1, control registers of power-
down state and peripheral modules are accessed in
an area from H'(FF)FF80 to H'(FF)FF87. Area from
H'(FF)FEA8 to H'(FF)FEAE is reserved.
1: When RELOCATE is 0, control registers of flash
memory are accessed in an area from H'(FF)FEA8
to H'(FF)FEAE. Area from H'(FF)FF80 to
H'(FF)FF87 is reserved.
When RELOCATE is 1, control registers of power-
down state and peripheral modules are accessed in
an area from H'(FF)FF80 to H'(FF)FF87. Control
registers of flash memory are accessed in an area
from H'(FF)FEA8 to H'(FF)FEAE.
2
R/(W)
I
C Extra Buffer Select
Specifies bits 7 to 4 of port A as output buffers similar
to SLC and SDA. These pins are used to implement an
2
I
C interface only by software.
0: PA7 to PA4 are normal input/output pins.
1: PA7 to PA4 are input/output pins enabling bus
driving.
R/W
Internal Clock Source Select 1 and 0
R/W
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with bits
CKS2 to CKS0 in TMR_0 or TMR_1 timer control
register (TCR). For details, see section 12.3.4, Timer
Control Register (TCR).
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