Reset Conditions - Renesas H8S/2100 Series Hardware Manual

Section 15 CIR Interface
CLK1 and
CLK0
φ
Setting
 φ
SUB
15.6

Reset Conditions

The range of initialization caused by a system reset, a software reset controlled by the SRES bit in
CCR1, or an abort is shown in table 15.6.
Table 15.6 Range of Initialization of CIR
HHMIN, HHMAX,
HLMIN, HLMAX,
DT0MIN, DT0MAX,
DT1MIN, DT1MAX,
CCR1, CCR2, CEIR
System reset Initialized
SRES software Retained
reset
Abort Retained
Rev. 1.00 May 09, 2008 Page 450 of 954
REJ09B0462-0100
BRR FLTCK
Setting Setting
H'00 Not divided
Divided by 2
Divided by 4
Divided by 8
RFMBN bit
in HHMIN
Initialized
Initialized
Retained
CIR Number of Stages
Sampling of Noise Canceler
Clock Circuit
31.3 µs
0
1
2
3
4
62.5 µs
0
2
4
125 µs
0
2
4
250 µs
0
2
4
CIRRDR CSTR
Initialized Initialized
Initialized Initialized
Retained Retained *
(CIRBUSY is
initialized.)
Width of
Noise
Cancellation
31.3 µs
62.5 µs
93.8 µs
125 µs
156 µs
62.5 µs
187.5 µs
312.5 µs
125 µs
375 µs
625 µs
250 µs
750 µs
1.25 ms
Sequence
Block BRR
Initialized Initialized
Initialized Initialized
Initialized Retained