Renesas H8S/2100 Series Hardware Manual page 511

6-bit single-chip microcomputer
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(5)
Data Reception
Figure 16.10 shows an example of the data reception flowchart.
Receive data ready interrupt
Read FLSR
BI = 1, FE = 1,
PE = 1, or OE = 1
Read receive FIFO
Read FLSR
DR = 0
(Transmission/reception standby flow)
[1]
Yes
Error processing
No
[2]
[3]
[4]
Figure 16.10 Example of Data Reception Flowchart
Section 16 Serial Communication Interface with FIFO (SCIF)
[1] When data is received, a receive data ready
interrupt occurs. Go to the data reception flow
by using this interrupt trigger.
[2] Confirm that the BI, FE, PE, and OE flags in
FLSR are all cleared. If any one of these flags
is set to 1, perform error processing.
[3] Read the receive FIFO.
[4] Check the DR flag in FLSR. When the DR flag
is cleared and all of the data has been read, data
reception is complete.
Rev. 1.00 May 09, 2008 Page 485 of 954
REJ09B0462-0100

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