Usage Notes - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Usage Notes

1. In master mode, if an instruction to generate a start condition is issued and then an instruction

to generate a stop condition is issued before the start condition is output to the I

condition will be output correctly.

2. Either of the following two conditions will start the next transfer. Pay attention to these

conditions when accessing ICDR.

 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to

 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to

3. Table 17.9 shows the timing of SCL and SDA outputs in synchronization with the internal

clock. Timings on the bus are determined by the rise and fall times of signals affected by the

bus load capacitance, series resistance, and parallel resistance.

Table 17.9 I

C Bus Timing (SCL and SDA Outputs)

SCL output cycle time

SCL output high pulse width

SCL output low pulse width

SDA output bus free time

Start condition output hold time

Retransmission start condition output

Stop condition output setup time

Data output setup time (master)

Data output setup time (slave)

Data output hold time

when IICX is 0, 12t

Output Timing

Section 17 I

Rev. 1.00 May 09, 2008 Page 543 of 954

C Bus Interface (IIC)

C bus, neither

REJ09B0462-0100