Renesas H8S/2100 Series Hardware Manual page 242

Section 9 8-Bit PWM Timer (PWMU)
The following shows the duty counter value and PWMU output timing.
Duty counter
H'FF
REGLAT
H'00
PWMUO
Figure 9.5 Duty Counter Value and PWMU Output Timing
If the PWMREG value is changed during PWM output, the PWMREG value is loaded into
REGLAT when the duty counter overflows (at the beginning of the next PWM cycle). The
following shows the PWMU output waveform when the PWMREG value is changed.
Duty counter
H'FF
REGLAT'
(value after write)
REGLAT
H'00
PWMUO
PWMREG
write signal
Figure 9.6 PWMU Output Waveform When PWMREG Value is Changed
Rev. 1.00 May 09, 2008 Page 216 of 954
REJ09B0462-0100