Renesas H8S/2100 Series Hardware Manual page 11

5.4 Interrupt Exception Handling .............................................................................................. 93
5.5 Trap Instruction Exception Handling................................................................................... 93
5.6 Stack Status after Exception Handling................................................................................. 94
5.7 Usage Note........................................................................................................................... 95
Section 6 Interrupt Controller ..............................................................................97
6.1 Features................................................................................................................................ 97
6.2 Input/Output Pins................................................................................................................. 99
6.3 Register Descriptions ......................................................................................................... 100
6.3.1 Interrupt Control Registers A to D (ICRA to ICRD)............................................ 101
6.3.2 Address Break Control Register (ABRKCR) ....................................................... 103
6.3.3 Break Address Registers A to C (BARA to BARC)............................................. 104
6.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................. 105
6.3.5 IRQ Enable Registers (IER16, IER) ..................................................................... 108
6.3.6 IRQ Status Registers (ISR16, ISR)....................................................................... 109
6.3.7 IRQ Sense Port Select Registers 16 (ISSR16)
IRQ Sense Port Select Registers (ISSR) ............................................................... 111
6.3.8 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMRB)
Wake-up Event Interrupt Mask Registers (WUEMRA, WUEMRB) ................... 112
6.3.9 Wake-Up Sense Control Register (WUESCRA, WUESCRB)
Wake-Up Input Interrupt Status Register (WUESRA, WUESRB)
Wake-Up Enable Register (WUEER)................................................................... 116
6.4 Interrupt Sources................................................................................................................ 119
6.4.1 External Interrupt Sources .................................................................................... 119
6.4.2 Internal Interrupt Sources ..................................................................................... 122
6.5 Interrupt Exception Handling Vector Tables ..................................................................... 123
6.6 Interrupt Control Modes and Interrupt Operation .............................................................. 131
6.6.1 Interrupt Control Mode 0...................................................................................... 133
6.6.2 Interrupt Control Mode 1...................................................................................... 135
6.6.3 Interrupt Exception Handling Sequence ............................................................... 138
6.6.4 Interrupt Response Times ..................................................................................... 139
6.7 Address Breaks .................................................................................................................. 140
6.7.1 Features................................................................................................................. 140
6.7.2 Block Diagram...................................................................................................... 140
6.7.3 Operation .............................................................................................................. 141
6.7.4 Usage Notes .......................................................................................................... 141
6.8 Usage Notes ....................................................................................................................... 143
6.8.1 Conflict between Interrupt Generation and Disabling .......................................... 143
6.8.2 Instructions for Disabling Interrupts..................................................................... 144
6.8.3 Interrupts during Execution of EEPMOV Instruction .......................................... 144
Rev. 1.00 May 09, 2008 Page xi of xxvi