Renesas H8S/2100 Series Hardware Manual page 708

6-bit single-chip microcomputer

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Table of Contents

Section 21 FSI Interface

FSI Command Write

If an LPC/FW memory write cycle for the FSI command space occurs, the FSI performs the FSI-

FLASH command write operation. Figure 21.12 shows an example of FSI Command write

CMDHBAR: H'EFFF

Figure 21.12 FSI Command Write Operation (Example)

As shown in figure 21.12, if a host address ranging from H'EFFF_F000 to H'EFFF_F00F is

accessed in LPC/FW memory write cycle while the CMDHBAR register is set to H'EFFF, the

write data is stored in FSICMDR, and then the CMDBUSY and FSICMDI flags in FSILSTR1 are

set to 1. In this case, an interrupt is requested according to the FSICMDIE state. Sync is not

returned if the host address to be input is out of the determined range. In FSI command write, no

wait cycle will be inserted to the LPC bus cycle. If the CMDBUSY flag is set to 1, Sync is not

returned during the operations other than FSI command read.

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REJ09B0462-0100

Host address

FSICMDR[7:0]

Command data (H'00 to H'FF)

Interrupt requests