Serial Data Reception (Asynchronous Mode) - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Section 14 Serial Communication Interface (SCI)

Serial Data Reception (Asynchronous Mode)

Figure 14.8 shows an example of the operation for reception in asynchronous mode. In serial

reception, the SCI operates as described below.

1. The SCI monitors the communication line, and if a start bit is detected, performs internal

synchronization, receives receive data in RSR, and checks the parity bit and stop bit.

2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR

is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this

time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF

flag remains to be set to 1.

3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to

RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.

4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive

data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt

request is generated.

5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is

transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is

generated. Because the RXI interrupt routine reads the receive data transferred to RDR before

reception of the next receive data has finished, continuous reception can be enabled.

Rev. 1.00 May 09, 2008 Page 390 of 954

REJ09B0462-0100

RXI interrupt

Figure 14.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit)

RDR data read and RDRF

flag cleared to 0 in RXI

interrupt service routine

(mark state)

ERI interrupt request

generated by framing