Lpc Interface Clock Start Request; Scif Control From Lpc Interface - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet

mode, the slave with interrupt sources requiring a request can also initiate an interrupt transfer

cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate interrupt

transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the power-down state.

In order for a slave to transfer an interrupt request in this case, a request to restart the clock must

first be issued to the host. For details see section 20.4.6, LPC Interface Clock Start Request.

LPC Interface Clock Start Request

A request to restart the clock (LCLK) can be sent to the host by means of the CLKRUN pin. With

LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the

transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt

request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to

the host. The timing for this operation is shown in figure 20.7.

Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a

different protocol, using the PME signal, etc.

Setting the SCIFE bit in HICR5 to 1 allows the LPC host to communicate with the SCIF. Then,

the LPC interface can access the registers of the module SCIF other than SCIFCR. For details on

transmission and reception, see section 16, Serial Communication Interface with FIFO (SCIF).

Pull-up enable

Driven by the slave processor

Figure 20.7 Clock Start Request Timing

Section 20 LPC Interface (LPC)

Driven by the host processor

Rev. 1.00 May 09, 2008 Page 639 of 954

REJ09B0462-0100