Renesas H8S/2100 Series Hardware Manual page 697

LPC Memory Read Cycles
State
Counts Content
14
Synchronization
15 Data 1
16 Data 2
17 Turn-around
(recovery)
18 Turn-around
Note: The number of wait cycles depends on the system.
*
Table 21.5 FW Memory Read/Write Cycles (Byte Transfer)
FW Memory Read Cycles
State
Counts Content
1 Start
2 Device select Host
3 Address 1
4 Address 2
5 Address 3
6 Address 4
7 Address 5
8 Address 6
9 Address 7
10 Size
11 Turn-around
(recovery)
12 Turn-around
13 Wait*
14
Synchronization
15 Data 1
16 Data 2
Driven by Value (3 to 0) Content
Slave 0000
Slave bit 3 to bit 0
Slave bit 7 to bit 4
Slave 1111
None ZZZZ
Driven by Value (3 to 0)
Host 1101
ID3 to ID0
Host bit 27 to bit 24
Host bit 23 to bit 20
Host bit 19 to bit 16
Host bit 15 to bit 12
Host bit 11 to bit 8
Host bit 7 to bit 4
Host bit 3 to bit 0
Host 0000
Host 1111
None ZZZZ
Slave 0110
Slave 0000
Slave bit 3 to bit 0
Slave bit 7 to bit 4
LPC Memory Write Cycles
Driven by
Turn-around None
Wait* Slave
Slave
Synchronization
Turn-around Slave
(recovery)
Turn-around None
FW Memory Write Cycles
Content Driven by Value (3 to 0)
Start Host
Device select Host
Address 1 Host
Address 2 Host
Address 3 Host
Address 4 Host
Address 5 Host
Address 6 Host
Address 7 Host
Size Host
Data 1 Host
Data 2 Host
Turn-around Host
(recovery)
Turn-around None
Wait* Slave
Slave
Synchronization
Rev. 1.00 May 09, 2008 Page 671 of 954
Section 21 FSI Interface
Value (3 to 0)
ZZZZ
0110
0000
1111
ZZZZ
1110
ID3 to ID0
bit 27 to bit 24
bit 23 to bit 20
bit 19 to bit 16
bit 15 to bit 12
bit 11 to bit 8
bit 7 to bit 4
bit 3 to bit 0
0000
bit 3 to bit 0
bit 7 to bit 4
1111
ZZZZ
0110
0000
REJ09B0462-0100