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Table 28.8 PS2 Timing
Conditions:
V
= 3.0 V to 3.6 V, V
CC
Item
KCLK, KD output fall time
KCLK, KD input data hold time
KCLK, KD input data setup time t
KCLK, KD output delay time
KCLK, KD capacitive load
Note:
*
When KCLK and KD are output, an external pull-up register must be connected, as
shown in figure 28.21.
(1) R eceive
φ
KCLK/KD*
(2) Transmit (a)
φ
KCLK/KD*
Transmit (b)
KCLK/KD*
Note: * KCLK : PS2AC, PS2BC
= 0 V, φ = 8 MHz to maximum operating frequency
SS
Symbol Min.
t
KBF
t
150
KBIH
150
KBIS
t
KBOD
C
b
t
t
KBIS
KBIH
KD : PS2AD, PS2BD
Figure 28.21 PS2 Timing
Section 28 Electrical Characteristics
Standard Value
Typ.
Max.
Unit
250
ns
ns
ns
450
ns
400
pF
t
KBF
Rev. 1.00 May 09, 2008 Page 933 of 954
Test
Conditions Remarks
Figure
28.21
t
KBOD
REJ09B0462-0100
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