Renesas H8S/2100 Series Hardware Manual page 290

6-bit single-chip microcomputer
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Section 10 16-Bit Timer Pulse Unit (TPU)
(b) When TGR is an input capture register
Figure 10.20 shows an operation example in which TGRA has been designated as an input capture
register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by
TGRA input capture has been set for TCNT, and both rising and falling edges have been selected
as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT
value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA
is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
TIOCA
TGRA
TGRC
Rev. 1.00 May 09, 2008 Page 264 of 954
REJ09B0462-0100
H'0532
Figure 10.20 Example of Buffer Operation (2)
H'0F07
H'09FB
H'0532
H'0F07
Time

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