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Section 17 I
C Bus Interface (IIC)
Master transmit mode
SCL
9
(master output)
SDA
A
(slave output)
SDA
(master output)
IRIC
IRTR
ICDRF
ICDRR
User processing
Figure 17.11 Example of Operation Timing in Master Receive Mode
SCL
7
8
(master output)
SDA
Bit 1
Bit 0
(slave output)
Data 2
SDA
(master output)
IRIC
IRTR
ICDRF
ICDRR
Data 1
[4] IRIC clear
User processing
Figure 17.12 Example of Stop Condition Issuance Operation Timing
Rev. 1.00 May 09, 2008 Page 530 of 954
REJ09B0462-0100
Master receive mode
SCL is fixed low until ICDR is read
1
2
3
Bit 7
Bit 6
Bit 5
Data 1
[1] TRS=0 clear
[2] ICDR read
[1] IRIC clear
(MLS = WAIT = 0)
SCL is fixed low until ICDR is read
9
1
2
Bit 7
Bit 6
[3]
A
[7] ICDR read
(Data 2)
[6] Set ACKB = 1
in Master Receive Mode (MLS = WAIT = 0)
4
5
6
7
8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Undefined value
[4] IRIC clear
(Dummy read)
SCL is fixed low until
stop condition is issued
3
4
5
6
7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Data 3
Data 2
[9] IRIC clear
SCL is fixed low until ICDR is read
1
9
2
Bit 7
Bit 6
[3]
Data 2
A
Data 1
[5] ICDR read
(Data 1)
Stop condition generation
8
9
Bit 0
[8]
A
Data 3
[10] ICDR read
(Data 3)
[11] Set BBSY=0 and
SCP=0
(Stop condition instruction issuance)
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