Section 9 8-Bit PWM Timer (PWMU)
• 8-bit pulse division mode
Operable at a maximum carrier frequency of 1.57 MHz (at 25 MHz operation)
Pulse output settable with a duty cycle from 0/16 to 15/16
PWM output enable/disable control, and selection of direct or inverted PWM output
Figure 9.1 shows a block diagram of the PWMU.
φ
φ/2
Clock
φ/4
selection
φ/8
Controller
[Legend]
PWMPRE:
PWM prescaler register
PWMREG:
PWM duty setting register
PRELAT:
Prescaler latch register
REGLAT:
Duty setting latch register
PWMUO:
PWM output waveform
PWME:
PWM output enable signal
Rev. 1.00 May 09, 2008 Page 198 of 954
REJ09B0462-0100
Clock
generator
Figure 9.1 Block Diagram of PWMU Timer
PRE
LAT
Transfer
control
circuit
REG
LAT
PWM counter/comparator
PWMCKCR:
PWM clock control register
PWMOUTCR:
PWM output control register
PWMMDCR:
PWM mode control register
PWMPCR:
PWM phase control register
Module
data bus
PWM
PRE
PWM
REG
PWMCKCR
PWMOUTCR
PWMMDCR
PWMPCR
PWMUO
PWME