Lpc Interface Serialized Interrupt Operation (Serirq) - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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LPC Interface Serialized Interrupt Operation (SERIRQ)

A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a

host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the

serialized interrupt transfer cycle generated by the host or a peripheral function, and a request

signal is generated by the frame corresponding to that interrupt. The timing is shown in figure

Drive source

H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample

H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle

The serialized interrupt transfer cycle frame configuration is as follows. Two of the states

comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level

at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The

recover state must be driven by the host or slave that was driving the preceding state.

Host controller

IOCHCK frame

Figure 20.6 SERIRQ Timing

Host controller

Rev. 1.00 May 09, 2008 Page 637 of 954

Section 20 LPC Interface (LPC)

REJ09B0462-0100