Renesas H8S/2100 Series Hardware Manual page 701

6-bit single-chip microcomputer

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Byte/Page-Program Instruction

If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 and the FSIDMYE bit in

FSILSTR1 are cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to

1, the SPI flash memory address and write data are stored in FSIAR and FSIWDR, respectively.

Then, the SPI flash memory address, the write data, and the Byte/Page-Program instruction which

is stored in FSIPPINS in advance are transferred to FSITDR. After SYNC (long wait) has been

returned, the TE bit in FSICR2 is set, starting the Byte/Page-Program instruction execution. When

the transmission has been completed, SYNC (Ready) and TAR are returned to the host. To

execute the Byte-Program instruction, byte transfer access in LPC memory write cycle or FW

memory write cycle should be performed. Figure 21.4 shows an example of data transfer to

FSITDR. Figure 21.5 shows the Page-Program instruction execution timing.

FSIWDR[31:0]

H'67_45_23_01

FSIPPINS[7:0]

Figure 21.4 Data Transfer to FSITDR (Example)

FSIWDR[31:24]

FSIWDR[23:16]

FSIWDR[15:8]

FSIAR[23:16]

Rev. 1.00 May 09, 2008 Page 675 of 954

Section 21 FSI Interface

REJ09B0462-0100