Register Descriptions - Renesas H8S/2100 Series Hardware Manual

Section 11 16-Bit Cycle Measurement Timer (TCM)
11.3

Register Descriptions

The TCMs have the following registers.
Table 11.2 Register Configuration
Channel Register Name
Channel 0 TCM timer counter_0
TCM cycle upper limit register_0 TCMMLCM_0
TCM cycle lower limit register_0
TCM input capture register_0
TCM input capture buffer
register_0
TCM status register_0
TCM control register_0
TCM interrupt enable register_0
Channel 1 TCM timer counter_1
TCM cycle upper limit register_1 TCMMLCM_1
TCM cycle lower limit register_1
TCM input capture register_1
TCM input capture buffer
register_1
TCM status register_1
TCM control register_1
TCM interrupt enable register_1
Channel 2 TCM timer counter_2
TCM cycle upper limit register_2 TCMMLCM_2
TCM cycle lower limit register_2
TCM input capture register_2
TCM input capture buffer
register_2
TCM status register_2
TCM control register_2
TCM interrupt enable register_2
Rev. 1.00 May 09, 2008 Page 294 of 954
REJ09B0462-0100
Abbreviation R/W
TCMCNT_0 R/W H'0000 H'FBC0
R/W H'FFFF H'FBC2
TCMMINCM_0 R/W H'0000 H'FBCC
TCMICR_0 R
TCMICRF_0 R
TCMCSR_0 R/W H'00
TCMCR_0 R/W H'00
TCMIER_0 R/W H'00
TCMCNT_1 R/W H'0000
R/W H'FFFF
TCMMINCM_1 R/W H'0000
TCMICR_1 R
TCMICRF_1 R
TCMCSR_1 R/W H'00
TCMCR_1 R/W H'00
TCMIER_1 R/W H'00
TCMCNT_2 R/W H'0000
R/W H'FFFF
TCMMINCM_2 R/W H'0000
TCMICR_2 R
TCMICRF_2 R
TCMCSR_2 R/W H'00
TCMCR_2 R/W H'00
TCMIER_2 R/W H'00
Initial
Value Address
H'0000 H'FBC4
H'0000 H'FBC6
H'FBC8
H'FBC9
H'FBCA
H'FBD0
H'FBD2
H'FBDC
H'0000 H'FBD4
H'0000 H'FBD6
H'FBD8
H'FBD9
H'FBDA
H'FBE0
H'FBE2
H'FBEC
H'0000 H'FBE4
H'0000 H'FBE6
H'FBE8
H'FBE9
H'FBEA
Data Bus
Width
16
16
16
16
16
8
8
8
16
16
16
16
16
8
8
8
16
16
16
16
16
8
8
8