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Bit
Bit Name
6
STS2
5
STS1
4
STS0
3
2
SCK2
1
SCK1
0
SCK0
[Legend]
X:
Don't care
Initial
Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Standby Timer Select 2 to 0
On canceling software standby mode or watch mode,
these bits select the wait time for clock stabilization
from clock oscillation start. Select a wait time of 8 ms
(oscillation stabilization time) or more, depending on
the operating frequency. Table 26.2 shows the
relationship between the STS2 to STS0 values and
wait time.
With an external clock, an arbitrary wait time can be
selected. For normal cases, the minimum value is
recommended.
Reserved
The initial value should not be changed.
System Clock Select 2 to 0
These bits select a clock for the bus master in high-
speed mode or medium-speed mode.
When making a transition to watch mode, these bits
must be cleared to B'000.
000: High-speed mode
001: Medium-speed clock: φ/2
010: Medium-speed clock: φ/4
011: Medium-speed clock: φ/8
100: Medium-speed clock: φ/16
101: Medium-speed clock: φ/32
11X: Setting prohibited
Rev. 1.00 May 09, 2008 Page 811 of 954
Section 26 Power-Down Modes
REJ09B0462-0100
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