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10.3.3
Timer I/O Control Register (TIOR)
The TIOR registers control the TGR registers. The TPU has four TIOR registers, two each for
channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the
TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST
bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the
counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this
setting is invalid and the register operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2
Bit
Bit Name
7
IOB3
6
IOB2
5
IOB1
4
IOB0
3
IOA3
2
IOA2
1
IOA1
0
IOA0
• TIORL_0
Bit
Bit Name
7
IOD3
6
IOD2
5
IOD1
4
IOD0
3
IOC3
2
IOC2
1
IOC1
0
IOC0
Initial
value
R/W
Description
0
R/W
I/O Control B3 to B0
0
R/W
Specify the function of TGRB.
0
R/W
0
R/W
0
R/W
I/O Control A3 to A0
0
R/W
Specify the function of TGRA.
0
R/W
0
R/W
Initial
value
R/W
Description
0
R/W
I/O Control D3 to D0
0
R/W
Specify the function of TGRD.
0
R/W
0
R/W
0
R/W
I/O Control C3 to C0
0
R/W
Specify the function of TGRC.
0
R/W
0
R/W
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 1.00 May 09, 2008 Page 235 of 954
REJ09B0462-0100
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