Renesas H8S/2100 Series Hardware Manual page 73

6-bit single-chip microcomputer
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Table 2.5
Logic Operations Instructions
Instruction
Size*
AND
B/W/L
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
Note:
*
Refers to the operand size.
B:
Byte
W: Word
L:
Longword
Table 2.6
Shift Instructions
Instruction
Size*
SHAL
B/W/L
SHAR
SHLL
B/W/L
SHLR
ROTL
B/W/L
ROTR
ROTXL
B/W/L
ROTXR
Note:
Refers to the operand size.
*
B:
Byte
W: Word
L:
Longword
Function
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
(Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
Function
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shifts are possible.
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shifts are possible.
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotations are possible.
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotations are possible.
Rev. 1.00 May 09, 2008 Page 47 of 954
REJ09B0462-0100
Section 2 CPU

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