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Section 8 I/O Ports
(5)
PC3/WUE11/TIOCD0/TCLKB
The pin function is switched as shown below according to the combination of the TPU channel 0
setting, the TPSC2 to TPSC0 bits in any of TCR_0 to TCR_2 of TPU, and the PC3DDR bit.
When the WUEMR11 bit in WUEMRA of the interrupt controller is cleared to 0, this pin
functions as the WUE11 input pin.
TPU channel 0 setting
PC3DDR
Pin function
Notes: 1. This pin functions as the TCLKB input pin when the TPSC2 to TPSC0 bits in any of
TCR_0 to TCR_2 are B'101. Also, when channel 0 is set to phase counting mode, this
pin functions as the TCLKB input pin.
2. This pin functions as the TIOCD0 input pin when the TPU channel 0 timer is set to
normal operation mode, or to phase counting mode while the IOD3 to IOD0 bits in
TIOR_0 are set to B'10xx. (x: Don't care)
(6)
PC2/WUE10/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the TPU channel 0
setting, the TPSC2 to TPSC0 bits in any of TCR_0 to TCR_2 of TPU, and the PC2DDR bit.
When the WUEMR10 bit in WUEMRA of the interrupt controller is cleared to 0, this pin
functions as the WUE10 input pin.
TPU channel 0 setting
PC2DDR
Pin function
Notes: 1. This pin functions as the TCLKA input pin when the TPSC2 to TPSC0 bits in any of
TCR_0 to TCR_2 are B'100. Also, when channel 0 is set to phase counting mode, this
pin functions as the TCLKA input pin.
2. This pin functions as the TIOCC0 input pin when the TPU channel 0 timer is set to
normal operation mode, or to phase counting mode while the IOC3 to IOC0 bits in
TIOR_0 are set to B'10xx. (x: Don't care)
Rev. 1.00 May 09, 2008 Page 182 of 954
REJ09B0462-0100
Input setting or initial value
0
PC3 input pin
TIOCD0 input pin*
WUE11 input pin/TCLKB input pin*
Input setting or initial value
0
PC2 input pin
TIOCC0 input pin*
WUE10 input pin/TCLKA input pin*
1
PC3 output pin
2
1
PC2 output pin
2
Output setting
TIOCD0 output pin
1
Output setting
TIOCC0 output pin
1
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