Transmitter Shift Register (Ftsr); Transmitter Holding Register (Fthr); Divisor Latch H, L (Fdlh, Fdll) - Renesas H8S/2100 Series Hardware Manual

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.3

Transmitter Shift Register (FTSR)

FTSR is a register that converts parallel data to serial data and then transmits the serial data from
the FTxD pin. When one frame transmission of serial data is completed, the next data is
transferred from FTHR. The serial data is transmitted from the LSB (bit 0).
FTSR cannot be written from the H8S CPU/LPC interface.
16.3.4

Transmitter Holding Register (FTHR)

FTHR is an 8-bit write-only register that stores serial transmit data. It is accessible when the
DLAB bit in FLCR is 0. Write transmit data while the THRE bit in FLCR is set to 1.
Data can be written to FTHR when the THRE bit is set with the FIFO disabled. If data is written to
FTHR when the THRE bit is not set, the data is overwritten.
While the THRE bit is set with the FIFO enabled, up to 16 bytes of data can be written. If data is
written with the FIFO full, the written data is lost.
Bit Bit Name
7 to 0 Bit 7 to
bit 0
16.3.5

Divisor Latch H, L (FDLH, FDLL)

The FDLH and FDLL are registers used to set the baud rate. They are accessible when the DLAB
bit in FLCR is 1. Frequency division ranging from 1 to (2
The frequency divider circuit stops when both of FDLH and FDLL are 0 (initial value).
• FDLH
Bit Bit Name
7 to 0 Bit 7 to
bit 0
Rev. 1.00 May 09, 2008 Page 460 of 954
REJ09B0462-0100
Initial Value R/W

W
Initial Value R/W
All 0 R/W
Description
Stores serial data to be transmitted.
The data is 16 bytes when the FIFO is enabled.
− 1) can be set with these registers.
16
Description
Upper 8 bits of divisor latch