Renesas H8S/2100 Series Hardware Manual page 620

Section 20 LPC Interface (LPC)
Initial
Bit Bit Name Value
4 ABRT 0
3 IBFIE3 0
2 IBFIE2 0
Rev. 1.00 May 09, 2008 Page 594 of 954
REJ09B0462-0100
R/W
Slave Host Description
R/(W)* 
LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
•
Writing 0 after reading ABRT = 1
•
LPC hardware reset
(LRESET pin falling edge detection)
•
LPC software reset (LRSTB = 1)
•
LPC hardware shutdown
(SDWNE = 1 and LPCPD pin falling edge
detection)
•
LPC software shutdown (SDWNB = 1)
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle

R/W IDR3 and TWR Receive Complete interrupt Enable
Enables or disables IBFI3 interrupt to the slave (this
LSI).
0: Input data register IDR3 and TWR receive
complete interrupt requests disabled
1: [When TWRIE = 0 in LADR3]
Input data register (IDR3) receive complete
interrupt requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive
complete interrupt requests enabled

R/W IDR2 Receive Complete interrupt Enable
Enables or disables IBFI2 interrupt to the slave (this
LSI).
0: Input data register (IDR2) receive complete
interrupt requests disabled
1: Input data register (IDR2) receive complete
interrupt requests enabled