Renesas H8S/2100 Series Hardware Manual page 289

6-bit single-chip microcomputer

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Examples of Buffer Operation

When TGR is an output compare register

Figure 10.19 shows an operation example in which PWM mode 1 has been designated for channel

0, and buffer operation has been designated for TGRA and TGRC. The settings used in this

example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at

compare match B. As buffer operation has been set, when compare match A occurs the output

changes and the value in buffer register TGRC is simultaneously transferred to timer general

PWM modes, see section 10.5.4, PWM Modes.

Figure 10.19 Example of Buffer Operation (1)

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 1.00 May 09, 2008 Page 263 of 954

REJ09B0462-0100