Renesas H8S/2100 Series Hardware Manual page 278

Section 10 16-Bit Timer Pulse Unit (TPU)
Internal data bus
H
Bus
L
master
Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
Internal data bus
H
Bus
L
master
Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
Internal data bus
H
Bus
L
master
Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]
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Bus interface
Bus interface
Bus interface
TCR
TMDR
TCR TMDR
Module
data bus
Module
data bus
Module
data bus