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Section 10 16-Bit Timer Pulse Unit (TPU)
Clock input
φ/1
Internal clock:
φ/4
φ/16
φ/64
φ/256
φ/1024
External clock:
TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
Channel 0:
TIOCA0
TIOCB0
TIOCC0
TIOCD0
Channel 1:
TIOCA1
TIOCB1
Channel 2:
TIOCA2
TIOCB2
[Legend]
TSTR:
Timer start register
TSYR:
Timer synchro register
TCR:
Timer control register
TMDR:
Timer mode register
Rev. 1.00 May 09, 2008 Page 224 of 954
REJ09B0462-0100
Timer I/O control registers (H, L)
TIOR (H, L):
Timer interrupt enable register
TIER:
Timer status register
TSR:
TImer general registers (A, B, C, D)
TGR (A, B, C, D):
Figure 10.1 Block Diagram of TPU
Internal data bus
A/D converter convertion
start signal
Interrupt request signals
Channel 0:
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1:
TGI1A
TGI1B
TCI1V
TCI1U
Channel 2:
TGI2A
TGI2B
TCI2V
TCI2U
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