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Section 25 Clock Pulse Generator
Table 25.3 External Clock Input Conditions
Item
External clock input pulse
width low level
External clock input pulse
width high level
External clock rising time
External clock falling time
Clock pulse width low level t
Clock pulse width high level t
EXTAL
The oscillator and duty correction circuit can adjust the waveform of the external clock input that
is input from the EXTAL pin.
When a specified clock signal is input to the EXTAL pin, internal clock signal output is
determined after the external clock output stabilization delay time (t
signal output is not determined during the t
maintain the reset state. Table 25.4 shows the external clock output stabilization delay time. Figure
25.6 shows the timing of the external clock output stabilization delay time.
Table 25.4 External Clock Output Stabilization Delay Time
Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V
Item
External clock output stabilization delay
time
includes a RES pulse width (t
Note:
t
*
DEXT
Rev. 1.00 May 09, 2008 Page 804 of 954
REJ09B0462-0100
VCC = 3.0 to 3.6 V
Symbol
Min.
t
12
EXL
t
12
EXH
t
EXr
t
EXf
0.4
CL
0.4
CH
t
EXH
t
EXr
Figure 25.5 External Clock Input Timing
DEXT
Symbol
t
*
DEXT
RESW
Max.
Unit Test Conditions
ns
ns
5
ns
5
ns
0.6
t
cyc
0.6
t
cyc
t
EXL
t
EXf
DEXT
cycle, a reset signal should be set to low to
Min.
Max.
500
).
Figure 25.5
Figure 28.4
V
× 0.5
CC
) has passed. As the clock
Unit
Remarks
µs
Figure 25.6
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