Programming/Erasing Interface Parameters - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Section 24 Flash Memory

Programming/Erasing Interface Parameters

The programming/erasing interface parameters specify the operating frequency, storage place for

program data, start address of programming destination, and erase block number, and exchanges

the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the

on-chip RAM area. The initial values of programming/erasing interface parameters are undefined

at a power-on reset or a transition to software standby mode.

Since registers of the CPU except for R0L are saved in the stack area during download of an on-

chip program, initialization, programming, or erasing, allocate the stack area before performing

these operations (the maximum stack size is 128 bytes). The return value of the processing result

is written in R0L. The programming/erasing interface parameters are used in download control,

initialization before programming or erasing, programming, and erasing. Table 24.6 shows the

usable parameters and target modes. The meaning of the bits in the flash pass and fail result

parameter (FPFR) varies in initialization, programming, and erasure.

Table 24.6 Parameters and Target Modes

A single byte of the start address of the on-chip RAM specified by FTDAR

(a) Download Control

The on-chip program is automatically downloaded by setting the SCO bit in FCCS to 1. The on-

chip RAM area to download the on-chip program is the 3-kbyte area starting from the start address

specified by FTDAR. Download is set by the programming/erasing interface registers, and the

download pass and fail result parameter (DPFR) indicates the return value.

Rev. 1.00 May 09, 2008 Page 732 of 954

REJ09B0462-0100

Initialization

On-chip RAM*