Table of Contents
Advertisement
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.12 TIORL_0 (channel 0)
Bit 7
Bit 6
IOD3
IOD2
0
0
1
1
0
1
[Legend]
×:
Don't care
Note: When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 1.00 May 09, 2008 Page 238 of 954
REJ09B0462-0100
Bit 5
Bit 4
IOD1
IOD0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
×
1
×
×
TGRD_0
Function
TIOCD0 Pin Function
Output
Output disabled
Compare
Initial output is 0 output
register*
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Input capture
Capture input source is TIOCD0 pin
register*
Input capture at rising edge
Capture input source is TIOCD0 pin
Input capture at falling edge
Capture input source is TIOCD0 pin
Input capture at both edges
Setting prohibited
Description
Advertisement
Table of Contents
