Cpu Operating Modes - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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CPU Operating Modes

This LSI operates in normal mode, which supports a maximum 16-Mbyte address space. The

mode is selected by the mode pins.

• Address Space

Linear access to a 16-Mbyte maximum address space is provided.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers.

• Instruction Set

All instructions and addressing modes can be used.

• Exception Vector Table and Memory Indirect Branch Addresses

In this LSI, the top area starting at H'00000000 is allocated to the exception vector table in 32-

bit units. One branch address is stored per 24 bits, ignoring the upper 8 bits (see figure 2.1).

For details of the exception vector table, see section 5, Exception Handling.

Exception handling vector 1

Exception handling vector 2

Exception handling vector 3

Exception handling vector 4

Exception handling vector 5

Figure 2.1 Exception Handling Vector Table

Exception handling

vector table

Rev. 1.00 May 09, 2008 Page 31 of 954

REJ09B0462-0100

Section 2 CPU