Table of Contents
Advertisement
Section 28 Electrical Characteristics
2
Table 28.9 I
C Bus Timing
Conditions:
V
= 3.0 V to 3.6 V, V
CC
Item
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse
elimination time
SDA input bus free time
Start condition input hold time
Retransmission start condition
input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
Note:
17.5 t
can be set according to the clock selected for use by the I
*
cyc
SDA0
SDAA to
SDAD
t
BUF
SCL0
SCLA to
SCLD
P*
Note: * S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Retransmission start condition
Rev. 1.00 May 09, 2008 Page 934 of 954
REJ09B0462-0100
= 0 V, φ = 8 MHz to maximum operating frequency
SS
Symbol Min.
t
SCL
t
SCLH
t
SCLL
t
Sr
t
Sf
t
SP
t
BUF
t
STAH
t
STAS
t
STOS
t
SDAS
t
SDAH
C
b
V
IH
V
IL
t
SCLH
t
STAH
S*
t
SCLL
t
t
Sr
Sf
t
SCL
2
Figure 28.22 I
C Bus Interface Input/Output Timing
Typ.
12
3
5
5
3
3
3
0.5
0
t
STAS
Sr*
t
SDAH
Test
Max.
Unit
Conditions
t
Figure
cyc
28.22
7.5*
300
ns
1
t
cyc
ns
400
pF
2
C module.
t
t
SP
STOS
P*
t
SDAS
Advertisement
Table of Contents
