Renesas H8S/2100 Series Hardware Manual page 655

LCLK
LFRAME
LAD3 to
Start
LAD0
1
Number of clocks
LCLK
LFRAME
Start
LAD3 to LAD0
ADDR
Cycle type,
direction,
and size
1 4
Figure 20.2 Typical LFRAME Timing
ADDR TAR
Cycle type,
direction,
and size
Figure 20.3 Abort Mechanism
Section 20 LPC Interface (LPC)
TAR Sync Data
2 1 2
Sync
Slave must stop driving
Too many Syncs
cause timeout
Rev. 1.00 May 09, 2008 Page 629 of 954
TAR Start
2 1
Master will
drive high
REJ09B0462-0100