Receive Abort - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Section 19 Keyboard Buffer Control Unit (PS2)

Receive Abort

This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard

side) in the event of a protocol error, etc. In this case, the system holds the clock low. During

reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when

the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is

an abort request from the system, and data transmission from the keyboard is aborted. Thus the

system can abort reception by holding the clock low for a certain period. A sample receive abort

processing flowchart is shown in figure 19.7, and the receive abort timing in figure 19.8.

Rev. 1.00 May 09, 2008 Page 568 of 954

REJ09B0462-0100

Figure 19.6 Transmit Timing

notification