Receive Timing; Operation During Data Reception - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Receive Timing

Figure 19.12 shows the receive timing.

KCLK (KCLKI)

Falling edge

Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode.

Figure 19.12 Receive Counter and KBBR Data Load Timing

If the KBS bit in KBCRH is set to 1 with other keyboard buffer control units in reception*, the

KCLK is automatically pulled down. Figure 19.13 shows receive timing and the KCLK.

Note: * Period from the first falling edge of KCLK to completion of reception (KBF = 1).

Figure 19.13 Receive Timing and KCLK

Section 19 Keyboard Buffer Control Unit (PS2)

Automatic I/O inhibit

Rev. 1.00 May 09, 2008 Page 573 of 954

REJ09B0462-0100