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Table 28.10 LPC Timing
Conditions:
V
CC
Item
Input clock cycle
Input clock pulse width (H)
Input clock pulse width (L)
Transmit signal delay time
Transmit signal floating delay
time
Receive signal setup time
Receive signal hold time
LCLK
LCLK
LAD3 to LAD0,
SERIRQ, CLKRUN
(transmit signal)
LAD3 to LAD0,
SERIRQ, CLKRUN,
LFRAME
(receive signal)
LAD3 to LAD0,
SERIRQ, CLKRUN
(transmit signal)
= 0 V, φ = 8 MHz to maximum operating frequency
= 3.0 V to 3.6V, V
SS
Symbol
t
Lcyc
t
LCKH
t
LCKL
t
TXD
t
OFF
t
RXS
t
RXH
Figure 28.23 LPC Interface (LPC) Timing
Min.
Typ.
30
11
11
2
7
0
t
t
LCKH
Lcyc
t
LCKL
t
TXD
t
t
RXS
RXH
t
OFF
Rev. 1.00 May 09, 2008 Page 935 of 954
Section 28 Electrical Characteristics
Max.
Unit
ns
11
28
REJ09B0462-0100
Test
Conditions
Figure
28.23
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