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Section 15 CIR Interface
15.3.6
Receive Data Register 0 to 7 (CIRRDR0 to CIRRDR7)
CIRRDR0 to CIRRDR7 are an 8-byte register that stores receive data, totaling to 8 bytes.
CIRRDR0 to CIRRDR7 share one byte of the register address. A receive data in CIRRDR should
be read after the CIR has finished data reception (CIRBUSY = 0). If CIRRDR is read during the
CIR reception (CIRBUSY = 1), an undefined value is read.
Bit
Bit Name
7 to 0
CIRRDR7 to
CIRRDR0
15.3.7
Header Minimum/Maximum High-Level Period Register (HHMIN and HHMAX)
HHMIN and HHMAX control the noise canceler circuit, and specify the minimum and maximum
high-level period for a header or repeat header, and low-level period for a stop.
• HHMIN
Bit
Bit Name
15 to 11 RFMBN4 to
RFMBN0
10
9 to 0
HHMIN9 to
HHMIN0
Rev. 1.00 May 09, 2008 Page 438 of 954
REJ09B0462-0100
Initial
Value
R/W
Description
H'00
R
Stores the CIR receive data.
Initial
Value
R/W
Description
All 0
R
Receive Byte Counter
The RFMBN value is incremented by 1 (+1) each
time a byte is received. However, when RFMBN
reaches B'01000, an overrun error occurs. At this
time, a receive data is not stored in CIRRDR.
When CIRRDR is read after the CIR has finished
receiving (CIRBUSY = 0), RFMBN is decremented
by 1 (−1). When CIRRDR is read while RFMBN =
B'00000, an undefined value is read. When CIRRDR
is read during the CIR reception, an undefined value
is read and RFMBN is not decremented.
0
R/W
Reserved
The initial value should not be changed.
All 0
R/W
Specifies the minimum high-level period for a header
or repeat header and the minimum low-level period
for a stop.
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