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21.3.8
FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7)
FSITDR stores a total of 8 bytes of transmit data. A total of 8 bytes of addresses, instructions, and
data items can be transferred continuously from FSITDR0 through FSITDR7 in this order to the
SPI flash memory. When LFBUSY is set to 1, a write to this register by the EC (this LSI) is
invalid. This register should not be set in the processing other than FSICMDI and FSIWI interrupt
processing.
Bit
Bit Name
7 to 0 bit 7 to bit 0 All 0
21.3.9
FSI Receive Data Register (FSIRDR)
FSIRDR stores a total of 4 bytes of receive data items continuously sent from the SPI flash
memory. This register should not be read in the processing other than FSICMDI interrupt
processing. Note that four bytes of receive registers share a single register address. A register to be
read will be determined according to the RBN bits in FSIBNR. When RBN = B'000, H'00 is read
out.
Bit
Bit Name
7 to 0 bit 7 to bit 0 All 0
R/W
Initial
Value
EC
Host Description
R/W
R/W
Initial
Value
EC
Host Description
R
These bits store transmit data.
These bits store receive data.
Rev. 1.00 May 09, 2008 Page 659 of 954
Section 21 FSI Interface
REJ09B0462-0100
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