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(7)
PC1/WUE9/TIOCB0
The pin function is switched as shown below according to the combination of the TPU channel 0
setting and the PC1DDR bit.
When the WUEMR9 bit in WUEMRA of the interrupt controller is cleared to 0, this pin functions
as the WUE9 input pin.
TPU channel 0 setting
PC1DDR
Pin function
Note:
This pin functions as the TIOCB0 input pin when the TPU channel 0 timer is set to
*
normal operation mode, or to phase counting mode while the IOB3 to IOB0 bits in
TIORH_0 are set to B'10xx. (x: Don't care)
(8)
PC0/WUE8/TIOCA0
The pin function is switched as shown below according to the combination of the TPU channel 0
setting and the PC0DDR bit.
When the WUEMR8 bit in WUEMRA of the interrupt controller is cleared to 0, this pin functions
as the WUE8 input pin.
TPU channel 0 setting
PC0DDR
Pin function
Note:
This pin functions as the TIOCA0 input pin when the TPU channel 0 timer is set to
*
normal operation mode, or to phase counting mode while the IOA3 to IOA0 bits in
TIORH_0 are set to B'10xx. (x: Don't care)
Input setting or initial value
0
PC1 input pin
TIOCB0 input pin*
Input setting or initial value
0
PC0 input pin
TIOCA0 input pin*
1
PC1 output pin
WUE9 input pin
1
PC0 output pin
WUE8 input pin
Rev. 1.00 May 09, 2008 Page 183 of 954
Section 8 I/O Ports
Output setting
TIOCB0 output pin
Output setting
TIOCA0 output pin
REJ09B0462-0100
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