Renesas H8S/2100 Series Hardware Manual page 669

Table 20.11 HIRQ Setting and Clearing Conditions when SCIF Channels are Used
Host Interrupt Setting Condition
HIRQi
Internal CPU sets the corresponding
(i = 1 to 15)
SERIRQ host interrupt request for the
SCIF in SIRQCR4 (for details, see the
description of SIRQCR4).
Changes in the SCIF input signal DCD are
detected.
Write 1 to IRQ1E1
No
No
Figure 20.8 HIRQ Flowchart (Example of Channel 1)
Slave CPU
ODR1 write
SERIRQ IRQ1 output
OBF1 = 0?
Yes
All bytes
transferred?
Yes
Clearing Condition
Reads FMSR and clears the DDCD
bit in FMSR
SERIRQ IRQ1
source clear
Rev. 1.00 May 09, 2008 Page 643 of 954
Section 20 LPC Interface (LPC)
Master CPU
Interrupt initiation
ODR1 read
Hardware operation
Software operation
REJ09B0462-0100