Spi Flash Memory Write Operation Mode - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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SPI Flash Memory Write Operation Mode

The write operation to the SPI flash memory in the LPC/FW memory write cycles can be

classified into the following four operation modes, depending or the state of FLDCT and

Table 21.7 SPI Flash Memory Write Operation in LPC/FW Memory Write Cycles

Selected Register

FSIWBUSY ← 1

FSIWBUSY ← 1

(Automatically

(Automatically

Section 21 FSI Interface

Control the write operation to the SPI

flash memory by the EC CPU. No wait

cycle is inserted to the LPC bus.

Confirm by FSIWBUSY whether or not

a write transfer has been completed.

Control the write operation to the SPI

flash memory by the EC CPU. Wait

cycles are inserted to the LPC bus.

Provision of wait cycles can be

canceled by clearing FSIWBUSY.

Control the write operation to the SPI

flash memory by the FSI. No wait cycle

is inserted to the LPC bus. Confirm by

LFBUSY whether or not a write

transfer has been completed.

Control the write operation to the SPI

flash memory by the FSI. Wait cycles

are inserted to the LPC bus. Provision

of wait cycles can be canceled by

clearing LFBUSY.

Rev. 1.00 May 09, 2008 Page 689 of 954

REJ09B0462-0100