Renesas H8S/2100 Series Hardware Manual page 712

Section 21 FSI Interface
STEP1
φ
FSIDMYE
Written by the CPU
FSICMDI
Cleared by the CPU
Cleared by the CPU
CMDBUSY
LPC_ADDR H'EFFF_F000
FSIAR[23:0]
TE
TBN
FSITDR3 to
FSITDR1
FSIINS
OBF
FSITEI
FSISS
FSICK
FSIDO
Figure 21.16 Execution Timing of SPI Flash Memory
Step 1:
1. Write an erasure setting command (Host).
2. Generate an FSICMDI interrupt request.
3. Set the FSIDMYE bit in FSILSTR1 to 1 and clear the FSICMDI and CMDBUSY bits in
FSILSTR1 to 0.
4. Complete the interrupt processing.
5. Check that the FSIDMYE bit in FSILSTR1 is set to 1 and that the CMDBUSY and FSICMDI
bits in FSILSTR1 are cleared to 0 (Host).
Step 2:
1. Perform a dummy write to the sector or block address to be erased (Host).
2. Store the SPI flash memory address and write data in the FSIAR register and FSIWDR
register, respectively*.
Note: * Use the data stored in FSIWDR if necessary on the user side.
Step 3:
1. Write an erasure setting command (Host).
2. Generate an FSICMDI interrupt request.
3. Clear the FSICMDI bit in FSILSTR1 to 0.
Rev. 1.00 May 09, 2008 Page 686 of 954
REJ09B0462-0100
STEP2
Cleared by the CPU
H'2325_4A76
H'06_4A76
Written by the CPU
STEP3
H'EFFF_F000
Written by the CPU H'4
Written by the CPU H'76-4A-06
Written by the CPU H'52
H'52->76->4A-> 06
Cleared by the CPU
Cleared by the CPU
Automatically cleared
H'00 (Automatically cleared)
Cleared by the CPU