Renesas H8S/2100 Series Hardware Manual page 16

12.6.2 Compare-Match Count Mode ............................................................................... 339
12.7 TMR_Y and TMR_X Cascaded Connection ..................................................................... 340
12.7.1 16-Bit Count Mode ............................................................................................... 340
12.7.2 Compare-Match Count Mode ............................................................................... 340
12.7.3 Input Capture Operation ....................................................................................... 341
12.8 Interrupt Sources................................................................................................................ 343
12.9 Usage Notes ....................................................................................................................... 344
12.9.1 Conflict between TCNT Write and Counter Clear ............................................... 344
12.9.2 Conflict between TCNT Write and Count-Up ...................................................... 344
12.9.3 Conflict between TCOR Write and Compare-Match............................................ 345
12.9.4 Conflict between Compare-Matches A and B ...................................................... 345
12.9.5 Switching of Internal Clocks and TCNT Operation ............................................. 346
12.9.6 Mode Setting with Cascaded Connection ............................................................. 348
12.9.7 Module Stop Mode Setting ................................................................................... 348
Section 13 Watchdog Timer (WDT) ................................................................. 349
13.1 Features.............................................................................................................................. 349
13.2 Input/Output Pins............................................................................................................... 351
13.3 Register Descriptions ......................................................................................................... 351
13.3.1 Timer Counter (TCNT)......................................................................................... 352
13.3.2 Timer Control/Status Register (TCSR)................................................................. 352
13.4 Operation ........................................................................................................................... 356
13.4.1 Watchdog Timer Mode......................................................................................... 356
13.4.2 Interval Timer Mode............................................................................................. 357
13.5 Interrupt Sources................................................................................................................ 358
13.6 Usage Notes ....................................................................................................................... 359
13.6.1 Notes on Register Access ..................................................................................... 359
13.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 360
13.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 360
13.6.4 Changing Value of PSS Bit .................................................................................. 360
13.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 360
Section 14 Serial Communication Interface (SCI)............................................ 361
14.1 Features.............................................................................................................................. 361
14.2 Input/Output Pins............................................................................................................... 363
14.3 Register Descriptions ......................................................................................................... 363
14.3.1 Receive Shift Register (RSR) ............................................................................... 364
14.3.2 Receive Data Register (RDR)............................................................................... 364
14.3.3 Transmit Data Register (TDR).............................................................................. 364
14.3.4 Transmit Shift Register (TSR) .............................................................................. 364
Rev. 1.00 May 09, 2008 Page xvi of xxvi