Section 18 Smbus 2.0 Interface (Smbus); Features - Renesas H8S/2100 Series Hardware Manual

Section 18 SMBus 2.0 Interface (SMBUS)

This LSI has a one-channel SMBus 2.0 interface (SMBUS). The SMBUS requires channel 0 of the
2
I C bus interface (IIC) as the communication module.
The SMBUS includes a hardware module that performs the packet error checking (PEC)
calculation.
This section explains the PEC calculation module. For details on the communication functions, see
the description of channel 0 in section 17, I
18.1

Features

• Conformance with the SMBus 2.0 interface. Supports transmission/reception formats that
include the PEC.
• Multiplexed usage of channel 0 of the I
• Includes a PEC calculation module, enabling high-speed CRC-8 calculation by hardware
CRC-8 (8bit Cyclic Redundancy Check): C(x) = x^8 + x^2 + x +1
φ
SDA0
SCL0
[Legend]
PECX: PEC calculation data entry register
PECY: PEC calculation data re-entry register
PECZ: PEC calculation result output register
2
C Bus Interface (IIC).
2
C bus module as the communication module
PEC calculation module
Communication
function module
calculator
(IIC channel 0)
Figure 18.1 Block Diagram of SMBus Interface
Section 18 SMBus 2.0 Interface (SMBUS)
PECX
PEC
PECY
PECZ
Rev. 1.00 May 09, 2008 Page 547 of 954
Internal data bus
Interrupt request
REJ09B0462-0100