Renesas H8S/2100 Series Hardware Manual page 376

Section 13 Watchdog Timer (WDT)
WOVI0
(Interrupt request signal)
Internal NMI
(Interrupt request signal*
Internal reset signal* 1
WOVI1
(Interrupt request signal)
Internal NMI
(Interrupt request signal*
Internal reset signal* 1
[Legend]
TCSR_0: Timer control/status register_0
TCNT_0: Timer counter_0
TCSR_1: Timer control/status register_1
TCNT_1: Timer counter_1
Notes: 1. The internal reset signal first resets the WDT in which the overflow has occurred first.
2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1.
The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from
that from WDT_1.
Rev. 1.00 May 09, 2008 Page 350 of 954
REJ09B0462-0100
Interrupt
control
Overflow
Reset
2 )
control
Interrupt
control
Overflow
Reset
2 )
control
Figure 13.1 Block Diagram of WDT
Clock
Clock
selection
TCNT_0 TCSR_0
Module bus
WDT_0
Clock
Clock
selection
TCNT_1 TCSR_1
Module bus
WDT_1
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
Bus
interface
φ/2
φSUB/2
φ/64
φSUB/4
φ/128
φSUB/8
φ/512
φSUB/16
φ/2048
φSUB/32
φ/8192
φSUB/64
φ/32768
φSUB/128
φ/131072
φSUB/256
Internal clock
Bus
interface