Renesas H8S/2100 Series Hardware Manual page 770

Section 24 Flash Memory
(1) Serial Interface Setting by Host
The SCI_1 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data,
one stop bit, and no parity.
When a transition to boot mode is made, the boot program embedded in this LSI is initiated.
When the boot program is initiated, this LSI measures the low period of asynchronous serial
communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and
adjusts the bit rate of the SCI_1 to match that of the host.
When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit
adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1
byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The
bit rate may not be adjusted within the allowable range depending on the combination of the bit
rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the
host and the system clock frequency of this LSI must be as shown in table 24.8.
Figure 24.7 Automatic-Bit-Rate Adjustment Operation
Table 24.8 System Clock Frequency for Automatic-Bit-Rate Adjustment
Bit Rate of Host
9,600 bps
19,200 bps
Rev. 1.00 May 09, 2008 Page 744 of 954
REJ09B0462-0100
Start
D0 D1 D2
bit
Measure low period (9 bits) (data is H'00)
D3 D4 D5 D6
System Clock Frequency of This LSI
8 to 25 MHz
8 to 25 MHz
D7 Stop bit
High period of
at least 1 bit