Operation; Baud Rate - Renesas H8S/2100 Series Hardware Manual

Section 16 Serial Communication Interface with FIFO (SCIF)
16.4

Operation

16.4.1

Baud Rate

The SCIF includes a baud rate generator and can set the desired baud rate using registers FDLH,
FDLL, and the CKSEL bit in SCIFCR. Table 16.6 shows an example of baud rate settings.
Table 16.6 Example of Baud Rate Settings
00
LCLK(33 MHz)
CKSEL1,
CKSEL0 divided by 18
FDLH,
Baud FDLL
rate (Hex) Error (%)
50 08F4 0.01 %
75 05F8 0.01 %
110 0412 0.03 %
300 017E 0.01 %
600 00BF 0.01 %
1200 005F 0.51 %
1800 0040 0.54 %
2400 0030 0.54 %
4800 0018 0.54 %
9600 000C 0.54 %
14400 0008 0.54 %
19200 0006 0.54 %
38400 0003 0.54 %
57600 0002 0.54 %
115200 0001 0.54 %
Rev. 1.00 May 09, 2008 Page 476 of 954
REJ09B0462-0100
01
System Clock
(25 MHz)
divided by 11
FDLH,
FDLL
(Hex) Error (%)
0B19 0.00 %
0766 0.00 %
050B 0.02 %
01D9 0.10 %
00ED 0.11 %
0076 0.31 %
004F 0.11 %
003B 0.31 %
001E 1.36 %
000F 1.36 %
000A 1.36 %
 
 
 
 
01
System Clock
(20 MHz)
divided by 11
FDLH,
FDLL
(Hex) Error (%)
08E1 0.01 %
05EB 0.01 %
0409 0.01 %
017B 0.06 %
00BD 0.21 %
005F 0.32 %
003F 0.21 %
002F 0.74 %
0018 1.36 %
000C 1.36 %
0008 1.36 %
0006 1.36 %
0003 1.36 %
0002 1.36 %
0001 1.36 %
01
System Clock
(10 MHz)
divided by 11
FDLH,
FDLL
(Hex) Error (%)
0470 0.03 %
02F6 0.06 %
0205 0.09 %
00BD 0.21 %
005F 0.32 %
002F 0.74 %
0020 1.36 %
0018 1.36 %
000C 1.36 %
0006 1.36 %
0004 1.36 %
0003 1.36 %
 
0001 1.36 %
 