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Section 21 FSI Interface
Step 1:
1. Write a status read setting command (Host).
2. Generate an FSICMDI interrupt request.
3. Clear the FSICMDI bit in FSILSTR1 to 0.
4. Check that the CMDBUSY bit in FSILSTR1 is set to 1 and that the FSICMDI bit in
FSILSTR1 is cleared to 0 (Host).
Step 2:
1. Perform the SPI flash memory status read instruction.
Set the RE bit in FSICR2 to 1.
Set the TBN bit in FSIBNR to 1-byte transfer and set the RBN bit in FSIBNR to 1-byte
reception.
Write the status read instruction to FSIINS (start the SPI flash memory status read
instruction execution).
2. Complete the interrupt processing.
Step 3:
1. Generate an FSIRXI interrupt request.
2. Write read data stored in FSIRDR to SPIGPR.
3. Clear the CMDBUSY bit in FSILSTR1 to 0.
4. Complete the interrupt processing
5. Check that the CMDBUSY and FSICMDI bits in FSILSTR1 are cleared to 0 (Host).
6. Read the SPI flash memory status from FSIGPR (Host).
Rev. 1.00 May 09, 2008 Page 688 of 954
REJ09B0462-0100
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