Condition-Code Register (Ccr) - Renesas H8S/2100 Series Hardware Manual

2.4.4

Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit Bit Name
7 I
6 UI
5 H
4 U
3 N
2 Z
Initial
Value R/W Description
1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to
1 at the start of an exception-handling sequence. For
details, refer to section 6, Interrupt Controller.
Undefined R/W User Bit or Interrupt Mask Bit
Can be read or written by software using the LDC, STC,
ANDC, ORC, and XORC instructions.
Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
Undefined R/W User Bit
Can be read or written by software using the LDC, STC,
ANDC, ORC, and XORC instructions.
Undefined R/W Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
Rev. 1.00 May 09, 2008 Page 37 of 954
REJ09B0462-0100
Section 2 CPU