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Section 6 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt request and starts execution of
the interrupt handling routine at the address indicated by the contents of the vector address in
the vector table.
IRQ0
Figure 6.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
Rev. 1.00 May 09, 2008 Page 134 of 954
REJ09B0462-0100
Program execution state
Interrupt generated?
Yes
An interrupt with interrupt
control level 1?
Yes
No
No
Yes
IRQ1
Yes
IBFI3
Yes
Save PC and CCR
Read vector address
Branch to interrupt handling routine
No
Yes
NMI
No
No
No
IRQ0
Yes
IRQ1
Yes
No
I = 0
Yes
I
1
Hold pending
No
IBFI3
Yes
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