Mode Setting With Cascaded Connection; Module Stop Mode Setting - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Section 12 8-Bit Timer (TMR)

Mode Setting with Cascaded Connection

If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock

pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the

counters will stop operating. Simultaneous setting of these two modes should therefore be

TMR operation can be enabled or disabled using the module stop control register. The initial

setting is for TMR operation to be halted. Register access is enabled by canceling the module stop

mode. For details, see section 26, Power-Down Modes.

Rev. 1.00 May 09, 2008 Page 348 of 954

REJ09B0462-0100